1. Field of the Invention
The present invention generally relates to integrated circuit memory devices and, more particularly, to Pseudo Static random access memory (PSRAM) devices operating in a burst access mode (“burst PSRAM”).
2. Description of the Related Art
In portable applications, such as handheld/wireless devices, the use of low power consuming memory is essential. A PSRAM device meets both low power consumption and high density requirements. A PSRAM, like a conventional dynamic random access memory (DRAM), contains dynamic memory cells but, in terms of interface and packaging, has the appearance of a static random access memory (SRAM). In the PSRAM, a refresh operation that is commonly required to maintain the stored information in dynamic memory cells is facilitated using internal means and, as such, is transparent to a system controller of the memory. Further, a PSRAM may operate in a burst mode. The burst mode enhances the speed of storing and retrieving information (or “data”). In the burst mode, specific functions must occur in a predetermined sequence. Such functions are generally performed in response to command signals produced by a system controller of the PSRAM device. The timing of the command signals is determined by a clock signal (CLK) and is registered either to an edge of the clock signal or occurring a predetermined time after the edge. To further increase data transmission rates, the PSRAM device may operate in a burst mode when an internal address counter increments an initial address to produce serial column locations. Additionally, in the burst mode, the burst PSRAM device may operate in fixed and variable latency modes where a value of the latency determines a minimal number of clock cycles that pass before a valid data output is present on a data bus.
In a single data-rate (SDR) burst PSRAM device, either a rising edge or a falling edge of the clock signal may be used as a data trigger point for the read and write operations. Herein, such operations are illustratively synchronized with the rising edge of the clock signal. Obtaining a high data transmission rate requires increasing the clock frequency or expanding a width of a system bus of the burst PSRAM device. In a fixed latency mode, burst PSRAM produces the valid data always in the programmed latency regardless of the internal condition of the device. In a variable latency mode, the burst PSRAM devices use a WAIT signal indicating to the system controller when valid data is present on a data bus in a Read cycle and when the memory is ready to accept data in a Write cycle. In the event that a Read or Write cycle collides with the execution of an internal refresh operation, the burst PSRAM asserts a few clock cycles of WAIT states until completion of the refresh operation. Otherwise, the read or write access would take place in the fastest time. The WAIT signal allows the data output and data input functions to take place at optimal time and, as such, increase operational speed of the burst PSRAM device.
FIG. 8 depicts a series of illustrative timing diagrams of signals which might appear in Read cycle on corresponding transmission lines of system and data buses of the SDR burst PSRAM device operating in a variable latency mode. In FIG. 8, the latency is illustratively equal to 3 clock cycles. Sub-series 802 and 804 include traces of the CLK signal, an Address signal, an Address Valid (ADV) signal, and a Chip Select (CS) signal and relate to a regular Read cycle and the Read cycle performed after the refresh operation, respectively.
In a double data rate (DDR) SDRAM device, both the rising and falling edges of the clock signal are trigger points for read and write operations. The DDR DRAM device doubles the peak data rate of comparable single data rate (SDR) SDRAM device using the same clock frequency. To address the increased timing accuracy requirements, a differential clock scheme is used in the DDR SDRAM devices. The DDR SDRAM uses a DQS signal which switching phase is edge-aligned with data output in Read cycles and center-aligned with data input in Write cycles to serve as a timing signal for valid data.
FIGS. 9 and 10 depict a series of illustrative timing diagrams of signals which might appear in Read and Write cycles, respectively, on corresponding transmission lines of system and data buses of a DDR SDRAM device operating in a fixed latency mode. In FIGS. 9 and 10, the latency is exemplary equal to 3 clock cycles, complimentary clock signal is shown with broken lines, and NOP, tDQSS(nom) and DM correspond to “no operation”, respectively. The rising and falling edges of the DQS signal are aligned to the edge of data outputs in Read cycle and to the center of the data inputs in Write cycle, respectively. Before the first valid data inputs or outputs, as well as after the last data inputs or outputs, the DQS signal asserts a logic low state and prepares buffers in the memory or system controller for receiving the data.
To facilitate a DDR feature in a memory device that is capable of operating in a variable latency mode by using the WAIT signal, such as PSRAM, the memory device needs the signal that may assert functionality of the DQS signal. However, an addition of the DQS signal increases the pin count of the memory and system controller and a width of the system bus, as well as may compromise timing relationship between the data strobe signal and the data.
Therefore, there is a need in the art for an improved method and circuit configuration for implementing a double data rate feature in a memory device capable of operating in a variable latency mode, such as a burst PSRAM device.